The present invention relates to computer apparatus. More particularly, it relates to a protective interrelation apparatus and method for multiple processor systems.
In some computer based control systems, a plurality of central processor units (CPU's) may work in conjunction with a common bulk memory means. In such an arrangement, there will, of necessity, be interface control means for controlling the access of the several CPU's to the common memory. It is a normal function of such interface control means to control the transfer of data between the bulk memory and the several CPU's under a normal priority routine. If, however, there occurs an emergency situation in one or more of the CPU's, valuable data may be lost or incorrect data transferred in the absence of protective measures to avoid said eventuality. For example, if the power supply should fail in one of the CPU's, there is a time frame of one millisecond in which all transactions relating to that CPU must be accomplished in order to preserve accurate data relative to that CPU.